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ASTM F1771-97
Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Techniquestandard by ASTM International, 02/10/1997
1.1 The techniques outlined in this standard are for the purpose of standardizing the procedure of measurement, analysis, and reporting of oxide integrity data between interested parties. This test method makes no representation regarding actual device failure rates or acceptance/rejection criteria. While some suggestions for data analysis are included in later sections of this test method, interpretation of results is beyond the scope of this standard. Any such interpretations should be agreed upon between interested parties prior to testing. For example, a variety of failure criteria are included to permit separation of so-called intrinsic and extrinsic oxide failures.
1.2 This test method covers the procedure for gaging the electrical strength of silicon dioxide thin films with thicknesses ranging from approximately 3 nm to 50 nm. In the analysis of films of 4 nm or less, the impact of direct tunneling on the current-voltage characteristics, and hence the specified failure criteria defined in 5.4, must be taken into account. Since oxide integrity strongly depends on wafer defects, contamination, cleanliness, as well as processing, the users of this test method are expected to include wafer manufacturers and device manufacturers.
1.3 This test method is not structure specific, but notes regarding options for different structures may be found in the appendix. The three most likely structures are simple planar metal-oxide semiconductor (MOS-capacitors) (fabricated or mercury probe), various isolation structures (for example, local oxidation of silicon (LOCOS)), and field effect transistors. This test method assumes that a low resistance ohmic contact is made to the backside of each wafer in each case. For a more detailed discussion of the design and evaluation of test structures for this test method, the reader is referred to the EIA/JEDEC Standard 35-1.
1.4 Failure criteria specified in this test method include both the fixed current limit (soft) and destructive (hard) types. In the past, use of a fixed current limit of 1
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